Im very excited to announce that next week Im conducting a LaTeX hands-on workshop organized by Women In Engineering affinity group in Tallinn University of Technology’s IEEE student branch. It’s becoming a tradition for me. I have done it twice before. Every year I try to provide this workshop for students who would like to …
This is a short post. Mostly because it’s not something complicated. Anyways…Today I wrote some small space invaders-ish program in python. You can find the code for it here. I’m trying to get the hang of curses. Here is what it ended up to be:
I always wanted to write game of life but never had time. So this week I wrote it in python. Here you can find the code. Its probably not the easiest way or most strait forward but its the first version. I wrote it in half an hour maybe. I eventually spent quite some time …
A while back in late 2016/early 2017, we faced the following problem: Let’s assume you have a set of online concurrent checkers (regardless of how they are generated!), and you want to deploy a subset of them (which can be as big as the original set) on a chip. You have two factors; Fault coverage …
So a while back I made a script which would generate a user defined test pattern for small circuits (or rather for small number of input combinations). The program gets the inputs as small chunks defined by the user (such as all ones, all zeros, one-hot, defined binary numbers etc.). I later use Itertools for making …
Simulator that does a bit more. I did a project a while back in May 2015. You can find the link to the project here. Back then I was thinking about making a simple scheduler for NoC based SoC. but it went a bit further and now turned into a simulator that also keeps a …
From Harvard to von Neumann The CPU initially had Harvard architecture; with a RAM for data and a ROM for instructions. During the process of development I figured that both of these memories are more or less acting like local cache for the actual memory. Since each memory responds in 1 clock cycle. So if …
Some updates about processor! I just finished implementing 67 instructions (not tested all of them obviously!). And these instructions are not covered: floating point stuff Co-processor stuff Atomic Read-Modify-Write BREAK and WAIT Anything Cache related Trap instructions Also, Division is implemented using “/” and “mod”. These are not synthesize-able and also for division I’m not …
Dependability Measures NoCs are usually very poor at handling faults. If you mess up, say a destination address in a header flit, chances are that your entire network will go bye bye! Anyways, if you look into the problem faults on the data path in the router, you can easily divide it into 2 parts, …
Ver II: Credit Based Flow Control After the first chip was out, we decided that its time to improve the router and there were two major drawbacks in this version that we targeted: The handshaking flow-control was performing very poorly (basically the network was working at a third of its capacity) The switch arbiters could …