The Processor (Part III)

From Harvard to von Neumann

The CPU initially had Harvard architecture; with a RAM for data and a ROM for instructions. During the process of development I figured that both of these memories are more or less acting like local cache for the actual memory. Since each memory responds in 1 clock cycle. So if I want to change them to actual memories, I need cache and some cache manager and having one set of these would be much easier to handle. So I merged both memories, and added preloading functionality to it.

modelsim’s file is more organized now.

Co-processor 0 and Exception Handling

Recently I added co-processor 0 functionality by just adding a register set inside the control unit of the system. These registers are accessible via MTC0 and MFC0 instructions. I’m not quite sure how to implement the rest of them though.

I also added exception handling. Once the exception happens I load the PC into EPC and load the PC with the contents of R2 (along with updating cause and status register of CP0). I flush the Pipe once an exception has occurred.

Testing a bit and implementing traps

I also ran some code on the CPU which essentially runs “a bootloader” and adds two numbers. I already found a couple of bugs there and fixed them. Things are looking promising now. We can push for more in-depth tests.
In the meantime I implemented 6 trap instructions, Which are not tested yet.
I need some documentation about how to implement cache and other co-processors. So if you know where I can find such info please let me know.


  • Cache is missing (including LL and SC instructions).
  • Floating point Co-processor is missing.
  • breaking multiplication and division into multi-cycle instruction to improve the critical path delay
  • Also I have to think about how to deal with aliases since apparently our synthesis tool cant handle them I can use some signals for them in the worst case scenario!
  • UART
  • GPIO