The Processor (Part II)

Some updates about processor!

I just finished implementing 67 instructions (not tested all of them obviously!). And these instructions are not covered:

  • floating point stuff
  • Co-processor stuff
  • Atomic Read-Modify-Write
  • BREAK and WAIT
  • Anything Cache related
  • Trap instructions

Also, Division is implemented using “/” and “mod”. These are not synthesize-able and also for division I’m not checking for division by zero!

There is something wrong with my memory system or my understanding of it. We have a memory with 1-clock cycle response time. Basically it will provide you data one clock cycle after it gets the address. However, this to me not really the behavior of  a memory, more close to what a huge cache will look like(one that is loaded with everything within memory). So at some point I have  to change my memory model and add cache as well.

Another point, I’m thinking about having a dual port memory for merging Instruction and data memories. I’m not sure about it though.

I checked and apparently the MIPS instructions actually assume that the processor executes 1 instructions after them regardless of jump being taken or not. this will help to avoid inserting bubbles into the pipeline!

Anyways, soon i will start testing.