A while back in late 2016/early 2017, we faced the following problem:
Let’s assume you have a set of online concurrent checkers (regardless of how they are generated!), and you want to deploy a subset of them (which can be as big as the original set) on a chip. You have two factors; Fault coverage and Area overhead of checker set. You would like to optimize the Area overhead of the checkers(by removing them) and keep the Fault coverage equal to the original value for the entire set.
To fix this, I made a tool(which we call it minimization framework) in python which contains a greedy heuristic algorithm along with a depth-first branch-and-bound algorithm. To generate different solutions I needed to incorporate different sets of checkers into the design. To achieve that I made a small program that gets the IDs of the checkers and adds the necessary code to the design (basically it was a combination of switches and prints). This is very similar to what I did in my master thesis.
With the help of my colleague, Behrad, we connected it to the synthesis tool and Turbo-Tester to calculate coverage and area overhead of the checker set in each optimization step.
Later on we published this work in this paper:
- S. P. Azad, B. Niazmand, A. K. Sandhu, J. Raik, G. Jervan and T. Hollstein, “Automated area and coverage optimization of minimal latency checkers,” 2017 22nd IEEE European Test Symposium (ETS), Limassol, Cyprus, 2017, pp. 1-2.