Simulator that does a bit more.

I did a project a while back in May 2015. You can find the link to the project here. Back then I was thinking about making a simple scheduler for NoC based SoC. but it went a bit further and now turned into a simulator that also keeps a system health view and acts upon component failures.

I have tried to document everything in the project’s wiki.
I model the application, architecture etc. using directed graphs of NetworkX library. Apparently they have changed their data structures recently and do not provide backward compatibility, which sort of makes the entire tool obsolete. However version 1.11 still works. My good friend Thilo  made this setup script. I have not tested it but plan to do soon.

Anyways, most of important stuff has been reported in the following publication:

  • S. P. Azad, B. Niazmand, P. Ellervee, J. Raik, G. Jervan and T. Hollstein, “SoCDep²: A framework for dependable task deployment on many-core systems under mixed-criticality constraints,” 2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Tallinn, 2016, pp. 1-6.

Library of Turn Models

I have written a small side tool using the same data structures in SoCDep². This tool enumerates all the 2D and 3D uniform turn-models and can test their reliability for user defined NoC size. Using this tool we figured out that there are 50 turn models that are deadlock free and also provide full connectivity in the network. My dear colleague Behrad generated latency, throughput and energy results and my other colleague Karl put all the results (whatever we found on 2D and 3D uniform turn-models) in this website. This later on resulted in the following publication:

  • S. P. Azad, B. Niazmand, K. Janson, T. Kogge, J. Raik, G. Jervan, T. Hollstein, “Comprehensive performance and robustness analysis of 2D turn models for network-on-chips,” 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, 2017, pp. 1-4.